hermess.tests.test_recur_sim_inverter

Byte-identical SIM baseline gates for the inverter models.

Exercise GridForming + GridFollowing (+ SGs) through the t=4.0 bus fault and compare the full state trajectory against the pickled references at atol=1e-6, for both network realizations:

• test_sim_line_dyn: line_dyn=True (ODE, cvodes).

• test_sim_alg: line_dyn=False (algebraic network / DAE, idas).

Any change to inverter state count, ordering, or numerics fails these instantly.

Functions

_assert_matches(→ None)
test_sim_line_dyn()
test_sim_alg()

Module Contents

hermess.tests.test_recur_sim_inverter._assert_matches(case: str, atol: float) → None

Parameters:

• case (str)

• atol (float)

Return type:

None

hermess.tests.test_recur_sim_inverter.test_sim_line_dyn()

hermess.tests.test_recur_sim_inverter.test_sim_alg()