hermess.tests.baselines.inverter_baseline
Shared configuration + runner for the inverter byte-identical baselines.
Single source of truth for the IEEE39_bus_inverter baseline runs, imported by
both create_baseline_inverter.py (which pickles the references) and the
test_recur_sim_inverter.py gates (which compare against them). Keeping the
config here prevents drift between baseline-creation and the tests. Two cases:
sim_ld– SIM,line_dyn=True(ODE; cvodes): 2 GridForming + 3 GridFollowing + 5 SGs through the t=4.0 bus fault. Run at the production output stepts=1e-4but stored decimated (everySIM_LD_STRIDE-th sample) so the pickle stays ~1 MB; a byte-identical refactor matches at every sample.sim_alg– SIM,line_dyn=False(algebraic network / DAE; idas).
Baselines store only the x_full numpy arrays, not the whole DaeSim objects:
under pytest’s pythonpath="hermess" + --import-mode=importlib,
system.DaeSim is reachable under two module paths, so whole-object pickling
raises “it’s not the same object”. The arrays are all the gates compare.
Attributes
Functions
Return the config for one baseline |
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Run one baseline |
Module Contents
- hermess.tests.baselines.inverter_baseline.FIXTURE_ROOT
- hermess.tests.baselines.inverter_baseline._BASE
- hermess.tests.baselines.inverter_baseline.SIM_LD_STRIDE = 50
- hermess.tests.baselines.inverter_baseline.T_END = 5.0
- hermess.tests.baselines.inverter_baseline.BASELINES
- hermess.tests.baselines.inverter_baseline._COMMON
- hermess.tests.baselines.inverter_baseline._INT_OPTS